1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a hierarchical bit line structure in which a bit line is formed of a plurality of interconnection layers including sub-bit lines and a main bit line.
2. Description of the Background Art
FIG. 61 shows arrangement of a memory cell array in a semiconductor memory device having a hierarchical bit line structure in the prior art. The structure of the semiconductor memory device shown in FIG. 61 is disclosed, for example, in "Experimental 4-Mbit Peripheral CMOS Dynamic RAM Using a Trench-Type Transistor Cell", Shichijo et al., Nikkei Electronics, Jul. 14, 1986.
Referring to FIG. 61, a memory cell array is divided into eight memory blocks M0-M7. X-decoders RD0-RD3 are disposed at a central area of the memory cell array. Each of X-decoders RD0-RD3 is commonly used by two memory blocks at laterally opposite sides of the same in the figure. For example, X-decoder RD0 is commonly used by memory blocks M0 and M4.
Sense amplifiers and Y-decoder blocks SY0-SY9 are disposed corresponding to memory blocks M0-M7. Y-decoders together with corresponding sense amplifiers (SA) in the blocks SY0, SY4, SY5 and SY9 are used by memory blocks M0, M3, M4 and M7, respectively. Each of the other Y-decoders/sense amplifiers (SA) blocks SY1-SY3 and SY6-SY8 are used by the memory blocks located at its opposite sides.
In operation, X-decoders RD0 and RD2 of even numbers or X-decoders RD1 and RD3 of odd numbers are activated. The activated X-decoders each select one word line in the corresponding two memory blocks. By setting the alternate memory blocks to the selected state, sensing operation can be performed by the sense amplifiers disposed at opposite sides of the selected memory blocks. After data of the selected memory cells are sensed by the sense amplifiers, one sense amplifier (SA) and Y-decoder block is activated, and a selected column is connected to an internal data line (I/O line), so that the data is written into or read from the selected memory cell.
FIG. 62 shows a specific structure of one memory block in the semiconductor memory device shown in FIG. 61. FIG. 62 shows two columns of memory cells and components related thereto.
In FIG. 62, each column of memory cells MC is divided into a plurality of (eight in FIG. 62) memory cell blocks B#0-B#7. In each column of the memory cells, memory cell blocks B#0-B#7 are provided with sub-bit lines SBLa0-SBLa7 and SBLb0-SBLb7, respectively. Word lines WL cross the sub-bit lines. In FIG. 62, 64 word lines WL0-WL63 are disposed in each of memory cell blocks B#0-B#7. Memory cells MC are disposed corresponding to the crossings of word lines and sub-bit lines. When a word line WL (WL generally represents WL0-WL63) is selected, memory cell MCa connected to sub-bit line SBLa (SBLa generally represents SBLa0-SBLa7) and memory cell MCb connected to sub-bit line SBLb (SBLb generally represents SBLb0-SBLb7) are brought simultaneously to the selected state. This arrangement of memory cells is similar to so-called "open bit line arrangement".
A main bit line MBLa or MBLb is disposed corresponding to each column of memory cells. Section select switches SWC0a-SWC7a and SWC0b-SWC7b, which correspond to memory cell blocks B#0-B#7, respectively, are provided on main bit lines MBLa and MBLb. Section select switches SWC0a and SWC0b-SWC7a and SWC7b are turned off in response to section select signals SEC0-SEC7, respectively. Segment select switches SWG0a and SWG0b-SWG7a and SWG7b, which are turned on in response to segment select signals SEG0-SEG7, respectively, each are provided at one end of a corresponding pair of sub-bit lines SBLa0 and SBLb0-SBL7a and SBL7b. When turned on, segment select switch SWGia (i=0-7) connects the corresponding sub-bit line SBLai to main bit line MBLa at one side of corresponding section select switch SWCia. When turned on, segment select switch SWGib connects the corresponding sub-bit line SBLbi to main bit line MBLb at the other side of corresponding section select switch SWCib.
Sense amplifiers SAa and SAb are disposed at opposite sides of main bit lines MBLa and MBLb. A dummy memory cell DMCa is provided at main bit line MBLa, and a dummy memory cell DMCb is provided at main bit line MBLb. Dummy memory cells DMCa and DMCb transfer their stored electric charges onto the corresponding main bit lines when dummy word lines DWL1 and DWL0 are selected, respectively. A quantity of electric charges stored in each of dummy memory cells DMCa and DMCb is equal to 1/2 of the sum of the quantity of stored charges of memory cell MC storing high-level data and the quantity of stored charges of memory cell MC storing low-level data. Operation of the structure shown in FIG. 62 will now be described below with reference to FIG. 63 which is an operation waveform diagram thereof.
In the standby state, segment select signals SEG0-SEG7 are inactive and hence low. Sub-bit lines SBLa0 and SBLb0-SBLa7 and SBLb7 are isolated or separated from main bit lines MBLa and MBLb. Section select signals SEC are high, and all of section select switches SWC0a and SWC0b-SWC7a and SWC7b are turned on. Main bit lines MBLa and MBLb are precharged to an intermediate potential such as Vcc/2.
Upon start of a memory cycle, an X-address signal (row address signal) is first applied. In accordance with the applied X-address, the memory cell block (selected memory cell block) to which the word line to be selected belongs is determined. Segment select signal SEG corresponding to the selected memory cell block rises to the high level, so that segment select switch SWG of the selected memory cell block is turned on.
After the segment select signal SEG rises to the high level and the sub-bit lines in the selected memory cell block are connected to main bit lines MBLa and MBLb, section select signal SEC falls to the low level. Thereby, main bit lines MBLa and MBLb each are divided into two portions. Segment select switches SWGia and SWGib are connected to one side of section select switch SWCia and the opposite side of section select switch SWCib, respectively. Therefore, sub-bit line SBLa is connected to sense amplifier SAa, and sub-bit line SBLb is connected to sense amplifier SAb. After the rising of segment select signal SEG to the high level, section select signal SEC is lowered to the low level so as to maintain symmetricity of parasitic capacitances related to sense amplifiers SAa and SAb. The section select signals provided corresponding to the nonselected memory cell blocks maintain the on-state because the section select signals SEC are high. For simplicity reasons, it is assumed in the following description that memory cell block B#0 is selected.
Section select signals SEC1-SEC7 corresponding to nonselected memory cell blocks B#1-B#7 are raised above the power supply voltage level. The reason for this boosting is to transmit signals on main bit lines MBLa and MBLb at a high speed.
Then, the word line is selected in accordance with the X-address signal, and the potential of the selected word line (e.g., WL0) rises to the high level. Data stored in memory cell MCa is transmitted onto sub-bit line SBLa0, and is transmitted via segment select switch SWG0a and main bit line MBLa to sense amplifier SAa. Likewise, data stored in the memory cell MCb connected to sub-bit line SBLb0 is transmitted via segment select switch SWG0b and main bit line MBLb to sense amplifier SAb. Also, dummy word lines DWL0 and DWL1 are simultaneously selected to have their potentials go to the high level. Then, sense amplifiers SAa and SAb are activated to perform the sensing operation, so that the potentials of main bit lines MBLa and MBLb change in accordance with the data stored in selected memory cells MCa and MCb. Thereafter, writing or reading of data is performed.
Then, the potential of segment select signal SEG0 corresponding to selected memory cell block B#0 is raised, and the potential of selected word line WL0 is raised. Thereby, data is rewritten or restored in memory cells MCa and MCb. After the restoring, the potential of the selected word line WL0 falls to the low level, and then, segment select signal SEG corresponding to the selected memory cell block B#0 is set to the power supply voltage level. The section select signals SEC1-SEC7 corresponding to the nonselected memory cell blocks maintain the raised level. In this state, sense amplifiers SAa and SAb are deactivated, main bit lines MBLa and MBLb are equalized, and selected sub-bit lines SBLa and SBLb are precharged to the intermediate potential.
Thereafter, all section select signals SEC0-SEC7 are maintained at the high level, i.e., power supply voltage Vcc level, and section select switches SWC0a and SWC0b-SWC7a and SWC7b are turned on. Main bit lines MBLa and MBLb are recovered from the divided state and are equalized to attain the intermediate potential. Thereafter, segment select signal SEG0 which has been selected is lowered to the low level, and segment select switches SWG0a and SWG0b are turned off, so that sub-bit lines SBLa0 and SBLb0 are isolated from main bit lines MBLa and MBLb.
As described above, the arrangement of memory cells with respect to the sub-bit lines is "open bit line arrangement", and the arrangement of memory cells with respect to the main bit lines is "folded bit line arrangement", whereby high density and high integration of memory cells as well as stable sensing operation are achieved.
FIG. 64 specifically shows a structure of the sense amplifier portion shown in FIG. 62. In FIG. 64, the main bit line is divided into two portions, and the divided main bit lines have different lengths depending on the position of the selected memory cell. Also, the sub-bit lines are connected to the main bit lines for transmitting data of the selected memory cell. For the above reasons, they are represented merely as bit lines BL and /BL.
In FIG. 64, sense amplifier SA includes n-channel MOS transistors Q7 and Q9 having gates and drains cross-coupled, and p-channel MOS transistors Q8 and Q10 having gates and drains cross-coupled. p-channel MOS transistors Q12 and Q13 which are in parallel to each other are interposed between power supply node Vcc and transistors Q8 and Q10. Transistors Q12 and Q13 are turned on in response to sense amplifier activation signals .phi.p1 and .phi.p2, respectively. The current driving ability of transistor Q12 is smaller than that of transistor Q13. n-channel MOS transistors Q14 and Q15 which are in parallel to each other are interposed between the ground potential node GND and transistors Q7 and Q9. Transistors Q14 and Q15 are turned on in response to sense amplifier activation signals .phi.n1 and .phi.n2, respectively. The current driving ability of transistor Q14 is larger than that of transistor Q15.
Bit lines BL and /BL are provided with an n-channel MOS transistor Q11 which is turned on in response to an equalizing signal E for equalizing potentials of bit lines BL and /BL, and are also provided with n-channel MOS transistors Q1 and Q2 which are turned on in response to equalizing signal E for transmitting a predetermined potential Vb1 (e.g., equal to Vcc/2) to bit lines BL and BL, respectively.
Between bit lines BL and /BL and sense nodes SNa and SNb of sense amplifier SA, there are disposed n-channel MOS transistors Q4 and Q3 which are turned off in response to a bit line transmission signal T for separating or isolating bit lines BL and /BL from sense nodes SNa and SNb, respectively. Between sense nodes SNa and SNb and internal data lines DB and /DB, there are disposed n-channel MOS transistors Q6 and Q5, respectively, which are turned on in response to a column select signal Y sent from the Y-decoder. The operation of the sense amplifier portion shown in FIG. 64 will be described below with reference to FIG. 65 showing its operation waveforms.
In the standby state, equalizing signal E is high, transistors Q1, Q2 and Q11 are on, and bit lines BL and BL are precharged and equalized to the intermediate potential Vb1. Bit line transmission signal T is high, transistors Q3 and Q4 are on, and thus sense nodes SNa and SNb have been precharged to intermediate potential Vb1.
Upon start of the memory cycle, equalizing signal E attains the low level, and transistors Q1, Q2 and Q11 are turned off. In this state, selection of the section, selection of the segment and selection of the word line are sequentially performed. When data of the memory cell connected to the selected word line is transmitted onto bit lines BL and /BL, sense amplifier activation signal .phi.n1 first rises to the high level, so that transistor Q14 is turned on. The potentials of sense nodes SNa and SNb are differentially amplified. The potential of one of sense nodes SNa and SNb, which is lower than that of the other, further falls. After sense amplifier activation signal .phi.n1 rises to the high level and the differential amplification is performed, bit line transmission signal T falls to the low level, and transistors Q3 and Q4 are turned off, so that bit lines BL and /BL are isolated from sense amplifier SA. A capacitance load to be driven by sense amplifier SA decreases, and the speed of sensing operation increases.
Then, sense amplifier activation signals .phi.n2 and .phi.p1 attain the high level and low level, respectively, and transistors Q12 and Q15 are turned on, so that charging/discharging of sense nodes SNa and SNb is performed and the potentials of sense nodes SNa and SNb are latched. Then, column select signal Y rises to the high level, and transistors Q5 and Q6 are turned on, so that signals of sense nodes SNa and SNb are transmitted to internal data lines DB and /DB, respectively.
After data is written or read, sense amplifier activation signal .phi.p2 attains the low level, and transistor Q13 is turned on. Transistor Q13 has a current supplying ability larger than that of transistor Q12. Sense amplifier activation signal .phi.p2 is set to the low level or active state during restoring. Thereby, a signal at the power supply potential Vcc level is reliably written into the selected memory cell. In the restoring operation, bit line transmission signal T has already risen to the high level, and the transistors Q3 and Q4 are on. Thereafter, sense amplifier activation signals .phi.p1, .phi.p2, .phi.n1 and .phi.n2 are deactivated, and then transistors Q1, Q2 and Q11 are turned on, so that equalizing/precharging of bit lines BL and /BL is performed. Then as already described, all section select signals SEC are set to the high level, and then all segment select signals SEG are set to the low level.
In the operation of sense amplifier SA, bit lines BL and /BL are isolated from sense amplifier SA, whereby the speed of sensing operation of sense amplifier SA increases due to decreased load capacitance.
In the hierarchical bit line structure described above, the stray capacitance (capacitance to ground) per unit length of sub-bit line directly connected to the memory cells is larger than the stray capacitance (capacitance to ground) per unit length of the main bit line, and a ratio therebetween is usually in a range from 5:1 to 10:1. The sub-bit line directly connected to the memory cells is connected to a diffusion layer of a memory cell transistor at a contact to the memory cell transistor. Therefore, the sub-bit line has a large parasitic capacitance because a junction capacitance between the diffusion layer and a substrate is large. Meanwhile, the main bit line is connected only to the sub-bit line, and is not directly connected to the memory cells, so that the main bit line has a small parasitic capacitance. In the hierarchical bit line structure, therefore, the entire length of the bit lines can be increased without increasing the parasitic capacitance per bit line. The sense amplifiers are provided only for the main bit lines, and it is not necessary to provide the sense amplifiers for the respective sub-bit lines, so that it is possible to reduce an area occupied by the bit line peripheral circuits such as sense amplifiers and precharge circuits, and thus the chip size can be reduced.
The hierarchical bit line structure described above also has such an advantage that a soft error rate can be reduced. The number of memory cells directly connected to one sub-bit line is small, and, e.g., 64 cells per sub-bit line. The sub-bit line is connected to the diffusion layers of the memory cell transistors at the contact to the memory cell transistors. If the diffusion layer collects carriers generated in the substrate due to incidence of .alpha.-rays, soft error in the bit line mode will be generated. In such collection of carriers is not generated in the main bit line, because the main bit line is not connected directly to a memory cell. In the hierarchical bit line structure, if a memory cell column is divided into four sub-bit lines, the number of memory cells which are directly connected to one bit line (formed of main bit line and sub-bit line) upon selection of the memory cell block is 64 and thus 1/4 of that in the nonhierarchical structure in which 256 memory cells are connected to one bit line. In the hierarchical bit line structure, therefore, the memory cells directly connected to one bit line can be small in number, so that the quantity of collected carriers is reduced and the possible soft error generating region is restricted in the memory cell block, resulting in reduction of the soft error rate.
In the operation of selecting the memory cell, a potential change .DELTA.V appearing on the hierarchical bit line including both the main bit line and the sub-bit line can be expressed by the following formula: EQU .DELTA.V=(Vcc/2(1/(1+Cb/Cs)) (1) EQU .about.(Vcc/2)(Cs/Cb) (1')
where Vcc represents the power supply level, Cb represents the stray capacitance of the hierarchical bit line, and Cs represents the capacitance of the capacitor in a memory cell.
The sense amplifier senses and amplifiers the potential change .DELTA.V. This amplifying operation of the sense amplifier is equivalent to charging/discharging of the parasitic capacitances at the sense nodes of the sense amplifier, and is performed by charging one of the sense nodes and discharging the other sense node. In this operation, if the parasitic capacitances of sense nodes are not balanced, the charging and discharging of sense nodes are performed at different speeds, so that the accurate sensing operation cannot be performed.
During the sensing operation in the conventional hierarchical bit line structure shown in FIG. 64, bit line transmission signal T is low, and bit lines BL and /BL are isolated from sense amplifier SA. Also in this case, however, bit line transmission signal T is lowered to the low level after sense amplifier activation signal .phi.n1 becomes high and transistor Q14 is turned on in sense amplifier SA to reduce the potential of one of sense nodes SNa and SNb, increasing the potential difference between sense nodes SNa and SNb. Therefore, if the load capacitances of sense nodes SNa and SNb are not balanced at this first stage in the sensing operation of the sense amplifier SA, accurate increase of the potential difference may be difficult, or a long time is required for increasing the potential difference, so that the sensing operation cannot be performed at a high speed.
The prior art employ a structure shown in FIG. 66 for overcoming the problem related to imbalance of the bit line capacitances to the sense amplifier.
FIG. 66 shows a connection mode of bit lines in the sensing operation of the prior art shown in FIGS. 61 to 64. In FIG. 66, a memory array block Mb is selected, and memory array blocks Ma and Mc are nonselected. In memory array block Mb, a sub-bit line SBLab is connected to a sense amplifier SAL, and a sub-bit line SBLbb is connected to a sense amplifier SAR.
In nonselected memory array blocks Mb and Mc, the operation selecting a memory cell block is similarly performed, so that sub-bit line SBLa is connected to sense amplifier SAL, and a divided main bit line MBLaa is similarly connected to sense amplifier SAL. A sub-bit line is not connected to divided main bit line MBLaa. A main bit line MBLac and a sub-bit line SBLac are connected to sense amplifier SAR, and a divided main bit line MBLbc is also connected thereto. In this manner, one segment in the nonselected memory array block is selected to equalize the bit line capacitances for sense amplifiers SAL and SAR.
In the above structure, however, it is necessary to turn on/off the segment switches and section switches also in the nonselected memory blocks, resulting in increase of the power consumption.
According to the structure utilizing the nonselected memory array blocks, as can be seen from the array arrangement in FIG. 61 it is impossible to maintain the balance between the bit line capacitances with respect to sense amplifiers SA contained in blocks SY0 and SY5 or blocks SY4 and SY9 when memory array blocks at the opposite ends, i.e., blocks M0 and M4 or blocks M3 and M7 are selected. In order to equalize the bit line capacitances in connection with all the sense amplifiers, a "dummy array" must be provided, which unnecessarily increases an area of the memory array.
In the structure shown in FIG. 66, since sub-bit lines of different memory array blocks are connected to the same sense amplifier, the feature of the "folded bit line arrangement", i.e., cancellation of noises of the same phase cannot be achieved, so that it is impossible to perform the accurate sensing operation.
If the bit line capacitances are not balanced, it is impossible to precharge accurately the hierarchical bit lines to the intermediate potential of Vcc/2, even if a equalizing/precharging transistor is provided, as described below.
As shown in FIG. 67, it is assumed that bit lines BL and /BL have parasitic capacitances of CBa and CBb, respectively. It is also assumed that bit line BL is charged to power supply potential Vcc, and bit line /BL is discharged to the ground potential level by the sensing operation. When equalizing signal E attains the high level, bit lines BL and /BL are electrically short-circuited. In this case, an equalized potential Vp of bit lines BL and /BL is expressed by the following formula: EQU Vp=Vcc.CBa/(CBa+CBb)
In the case of CBa&lt;CBb, precharge potential Vp is lower than intermediate potential of Vcc/2. Precharging to the intermediate potential of Vb1 (=Vcc/2) can be performed by precharge transistors Q1 and Q2 shown in FIG. 64. However, it is necessary to supply a current from an intermediate potential generating circuit, resulting in increase of the power consumption. To the contrary, in the case of CBa&gt;CBb, precharge potential Vp is higher than intermediate potential of Vcc/2. In this case, turn-on of precharge transistors Q1 and Q2 merely stops supply of electric charges to bit lines BL and /BL, and hierarchical bit lines BL and /BL maintain precharge potential Vp higher than the intermediate potential. Therefore, an accurate reference voltage cannot be generated in the next operation of reading data from the memory cell, and data of the memory cell cannot be accurately sensed and amplified.
If the Y-decoder block is provided for each memory array block, as is done in the array arrangement shown in FIG. 61, the number of Y-decoder blocks and thus the area occupied by the array increase as the storage capacity and hence the number of array blocks increase.
FIG. 68 shows another structure of the conventional semiconductor memory device. The structure of the semiconductor memory device shown in FIG. 68 is disclosed, for example, in "Bidirectional Matched Global Bit Line Scheme for High Density DRAMs", J. H. Ahn et al., 1993 Symposium on VLSI Circuit, Digest of Technical Papers, May 1993, pp. 91-92.
In FIG. 68, a memory array is divided into eight memory array blocks M#0-M#7. There are provided global bit lines which are common to memory array blocks M#0-M#7, and local bit lines are provided in each memory array block. Sense amplifier groups SAGU and SAGB are disposed at opposite sides of the memory array and are adjacent to outer sides of memory array blocks M#0 and M#7, respectively. There are also disposed Y-decoders YDU and YDB adjacent to sense amplifier groups SAGU and SAGB.
There are provided switch circuits (SW#0-SW#3), each of which is disposed between two memory array blocks forming one unit. Each of switch circuits SW#0-SW#3 includes separation switches provided at the global bit lines and switching elements for connecting the global bit lines to the local bit lines included in the corresponding memory array block, as will be described later.
FIG. 69A schematically shows a structure of a pair of global bit lines in the device shown in FIG. 68. Global bit lines GBLa and GBLb are provided with section select switches SWC0-SWC4 which are turned off in response to section select signals SEC (SEC0-SEC4), respectively. Sub-bit lines SBLa (SBLa0-SBLa7) and SBLb (SBLb0-SBLb7) are provided with segment select switches SWGa (SWGa0-SWGa7) and SWGb (SWGb0-SWGb7), respectively, which are turned on in response to segment select signals SEG (SEG0-SEG4). Segment select switches SWGa and SWGb are adapted to connect the paired sub-bit lines SBLa and SBLb to portions of the corresponding global bit line GBLa or GBLb located at opposite sides of the corresponding section select switch SEC.
For example, in memory array block M#0, sub-bit line SBLa0 is connected to one terminal of section select switch SWC0 via segment select switch SWGa0, and sub-bit line SBLb0 is connected to the other terminal of section select switch SWC0 via segment select switch SWGb0. According to this structure, when a memory array block M#0, or M#2, . . . at an even position is selected, data of the selected memory cell is transmitted to global bit line GBLa. When a memory array block M#1, or M#3, . . . at an odd position is selected, data of the selected memory cell is transmitted to global bit line GBLb. Now, the operation will be described briefly.
It is assumed that word line WL included in memory array block M#0 is selected. In this case, section select signal SEC0 attains the low level, and section select switch SWC0 is turned off. Other section select signals SEC1-SEC4 maintain the high level, and section select switches SWC1-SWC4 are on.
Then, segment select signal SEG0 attains the high level, and segment select switches SWGa and SWGb are turned on. In memory array block M#1, segment select switches SWGa1 and SWGb1 are turned on at this time.
Sub-bit line SBLa0 is connected to sense amplifier SAa, and sub-bit line SBLb0 is connected to sense amplifier SAb. Sub-bit line SBLa1 is connected to sense amplifier SAa, and sub-bit line SBLb1 is connected to sense amplifier SAb.
FIG. 69B is an electrically equivalent circuit diagram showing a connection mode of the sub-bit lines and sense amplifiers. As shown in FIG. 69B, sub-bit line SBLa1 functions as a reference bit line with respect to sub-bit line SBLa0, and sub-bit line SBLb1 functions as a reference bit line with respect to sub-bit line SBLb0. Sense amplifier SAa senses and amplifies data of memory cell MCa transmitted to sub-bit line SBLa0, and sense amplifier SAb senses and amplifies data of memory cell MCb transmitted to selected sub-bit line SBLb0. In the structure shown in FIGS. 69A and 69B, the bit line capacitances are balanced as for sense amplifiers SAa and SAb. Similarly to the prior art already described, this structure presents such a problem that the lengths of hierarchical bit lines and thus the load capacitances of sense amplifiers change depending on the position of the selected word line. The change of bit line capacitances will now be described briefly.
FIGS. 70A and 70B schematically show connection modes of the sense amplifiers and sub-bit lines. When word line WL is selected as shown in FIG. 70A, sub-bit line SBLa is connected to sense amplifier SAa, and sub-bit line SBLb is connected to sense amplifier SAb. In this state, the bit line capacitance CB1 is obtained with respect to the sense node of sense amplifier SAa, and the bit line capacitance CB2 is obtained with respect to the sense node of sense amplifier SAb. When bit line capacitance CB1 or CB2 changes, potential change .DELTA.V appearing at the sense node of sense amplifier changes as represented by the aforementioned formula (1). The change of capacitances CB1 and CB2 is not caused by the parasitic capacitances of sub-bit lines SBLa and SBLb, but is caused by the fact that the lengths of main bit lines change depending on the position of the selected word line.
As shown in FIG. 70B, the bit line capacitance with respect to sense amplifier SAa takes the minimum value CBmn when the memory array block which is nearest to the sense amplifier SAa is selected. In this case, bit line capacitance CB2 with respect to the other sense amplifier SAb takes the maximum value CBmx because the main bit line (global bit line) has the maximum length. A larger potential difference at the sense nodes of sense amplifier is desired for the accurate sensing operation. A larger bit line capacitance causes delay in signal transmission. Therefore, the timing of starting the sensing operation of sense amplifiers SAa and SAb depends on the maximum bit line capacitance CBmx, so that the sensing operation cannot be started at an early timing, resulting in a problem that the access time increases.
FIG. 71 shows a structure of the switch circuit shown in FIG. 69. In FIG. 71, global bit lines GBLa and GBLb each are divided into two portions, and one of the paired divided global bit lines functions as the reference bit line, so that the global bit lines are indicated by reference characters GBL and /GBL. FIG. 71 shows the structure of switch circuit disposed between memory array blocks M#0 and M#1.
In FIG. 71, the switch circuit includes section select switches SWC0 disposed in series between global bit lines BGLA and GBLB and between /GBLA and /GBLB. Section select switches SWC0 are turned off in response to section select signal SEC (i.e., an inverted signal /SEG0 of segment select signal SEG0).
The switching circuit further includes segment select switches SWGa0 and SWGb0 which are turned on to connect sub-bit lines SBLa0 and SBLb0 to global bit lines GBLA and GBLB in response to segment select signal SEG0, respectively, and segment select switches SWGa1 and SWGb1 which are turned on to connect sub-bit lines SBLa1 and SBLb1 to global bit lines /GBLA and /GBLB in response to segment select signal SEG0, respectively.
Sub-bit lines SBLa0 and SBLb0 as well as SBLa1 and SBLb1 are provided with precharging/equalizing transistors QE0 and QE1 as well as QE2 and QE3 which are turned on to transmit the intermediate potential of Vcc/2 to the corresponding sub-bit lines in response to section select signal SEC (/SEG0).
As can be seen from the structure of switch circuit shown in FIG. 71, the switch circuit has an extremely complicated layout, and it is difficult to dispose the switch circuit with a sufficient margin if the bit line pitch is small, which remarkably impedes the high integration, because a contact region required for connecting the switching element to the global bit line or sub-bit line is wider than the diffusion region of the switching transistor and thus occupies a large area).
FIG. 72 shows arrangement of global bit lines disclosed in the aforementioned reference of 1993 Symposium on VLSI Circuit. As shown in FIG. 72, global bit line crossing regions are provided at switch circuit formation regions, and are located alternately in the column and row directions with respect to the global bit line pairs. This reference merely discloses that the crossing regions are provided at the switch circuit formation regions, and does not disclose a specific structure for providing switching elements thereat. The crossing portions are provided at the global bit line pairs for the purpose of reducing the coupling noises caused by the coupling capacitance between adjacent global bit lines.
However, provision of the crossing portions at the global bit line pairs complicates the structure of switching circuits, resulting in a problem that the switch circuits occupy a large area if the crossing regions of global bit lines are located at the regions of switching circuits.